1. Field of the Invention
The present invention relates to semiconductor devices that utilize transistor-transistor logic (TTL) output circuitry in combination with internal non-TTL circuitry. More particularly, the present invention relates to an improved logic level translator for eliminating the large surge currents which occur during switching causing large power supply transients that add considerably to the noise generated by the translator circuit.
2. Description of the Prior Art
Several families of logic circuits are available for use in implementing the logic functions central to the operation of high speed computers and digital equipment. These logic circuit families differ in circuit characteristics such as speed of operation, logic levels, noise immunity (noise margin), power dissipation and fan-out capability. Development of logic circuitry has evolved from the first logic family designs - resistor-transistor logic (RTL) and diode-transistor logic (DTL) - to transistor-transistor logic (TTL), emitter-coupled logic (ECL) and integrated-injection logic (I.sup.2 L) circuit designs, with each step in this evolution bringing faster switching speeds, lower power dissipation and greater noise immunity. The superior switching speed of the later designs (TTL and ECL) has made the RTL and DTL families obsolete.
The continuing effort to reduce switching speeds led to the development and use of the Schottky Diode, which has a lower forward voltage at a given current level than the conventional diffused (p-n) diode. The Schottky diode also has a lower storage time, hence a lower fall time, and thus it is inherently faster than a conventional diode. Using Schottky diodes as clamps on individual transistors (connected from base to collector) prevents heavy transistor saturation caused by excess charge stored in the transistor's base region, thus reducing switching delay. In this manner, the Schottky TTL design achieves greater switching speed with no increase in power dissipation over standard TTL.
Additional design techniques, such as increasing resistance and adding a Darlington booster stage to the TTL output, provide a reduction in power dissipation. However, this decrease in power dissipation is accompanied by an increase in propagation delay.
The combination of low-power technology and Schottky clamping resulted in the low-power Schottky TTL integrated circuit, now firmly established as a standard logic configuration for high performance systems. For applications in which speed and low power are critical, low-power Schottky TTL gives the lowest product of propagation delay and power dissipation (speed-power product) of any of the TTL variations.
Low-power gates have the further advantage of increased fan out capability over standard gates, ie., a greater number of gate inputs can be driven by a lower power gate output, without affecting its logic level output.
Further improvements in switching speed were achieved with the development of the emitter-coupled logic (ECL) circuit. ECL is a form of current-mode logic, i.e., logic in which unsaturated transistors operate from a constant current source that is switched at very high speed from one transistor to another. The basic ECL structure is configured such that the emitters of two transistors are connected to a single current-carrying resistor in such a way that only one transistor conducts at a time. The logic state of the output depends on which transistor is conducting. The ECL design eliminates transistor saturation in order to increase switching speed. An ECL circuit requires a relatively small logic swing (output voltage change between high and low logic levels) which also contributes to greater switching speed. For applications in which very high switching speed is the sole critical parameter, ECL excels over all other configurations.
In addition to switching speed and power dissipation, noise margin is another circuit characteristic which is an important design consideration. Excessive noise on a supply bus line or a ground bus line of an integrated circuit device could affect the input of an internal logic circuit, temporarily causing that circuit to change states, resulting in an erroneous output. Noise margin is essentially a measure of the maximum noise voltage tolerable at the gate input to guarantee preclusion of false switching. Specifically, noise margin is defined as the voltage difference between the guaranteed DC output voltage of a particular logic circuit and its worst-case input threshold voltage (i.e., the minimum input voltage required to produce said guaranteed output voltage). Thus, it is apparent that noise margin is related to the difference between the high and low logic levels of a particular circuit. This difference, termed the logic swing, is defined as the difference between the logical-HIGH output voltage and the logical-LOW output voltage. Therefore, the smaller the logic swing is, the smaller the noise margin will be.
To maximize system performance, circuits from different logic families can be used in combination, with each circuit being selected according to its intended function considered in conjunction with its performance characteristics. In pulse-counting applications, for example, ECL circuits can be used in the initial counting stages where high speed is necessary. Once the frequency is divided it is economical to use slower logic circuits for the lowerspeed counting states. However, since TTL has become the industry standard for input/output compatability of integrated circuit devices, TTL circuits must be placed at the inputs and outputs of any internal non-TTL circuitry used within an integrated circuit. Furthermore, because different logic families have different logic levels, interface circuitry is required when circuits from different logic families are interconnected. Noise problems, however, have been encountered with such configurations. More specifically, the TTL output stage of the interface ("translator") circuitry generates noise pulses ("spikes") when switching, which can cause erroneous state changes by the non-TTL circuit to which the translator circuit is connected.